A serializer-deserializer (SerDes, or SERDES) is a pair of functional blocks used for high-speed communication between two systems, such as two application-specific integrated circuits (ASICs), across a limited input/output link between the two systems. Generally, each system will include at least one SerDes transmitter and at least one SerDes receiver, thereby allowing bidirectional communication, although some such SerDes will use only transmitters on the first system and only receivers on the second system.
A SerDes communicates across the input/output link using a high-speed digital signal. This signal is transmitted by the SerDes transmitter, and the characteristics of the signal are determined by various system parameters set by the SerDes Transmitter and/or receiver. These system parameters may include sampling timing offset; sampling vertical (voltage) offset; amount of gain provided by a continuous time linear equalizer (CTLE); amount of gain provided by a decision feedback equalizer (DFE); power consumption; and potentially others. The settings used for these system parameters by the transmitter and/or receiver affect the various characteristics of the signal received at the other end of the link at the receiver: amplitude, phase, noise, and so forth.
As SerDes data rates have increased with advances in communication technology, signal integrity has become more difficult to maintain across the input/output link. A variety of impairments (ISI, Integrated Crosstalk Noise, random noise, etc.) can affect the transmission of data over a link, and result in signal-to-noise ratio (SNR) being compromised and errors appearing at the receiver.
Accordingly, newer standards for SerDes recommend the use of Forward Error Correction (FEC) at data rates of 25 Gbps (gigabit per second); at data rates above 25 Gbps, or where PAM4 modulation is used, FEC becomes mandatory. Forward Error Correction is a system for detecting and correcting errors in the coded data stream received by the receiver of a SerDes.
In a typical FEC configuration, a redundancy overhead is added to the payload data at the transmitter side, using a certain coding. The coding allows for errors to be detected and corrected, up to a certain threshold (which depends on the amount and type of coding overhead and type of error pattern).
The rate of received errors is referred to as the Bit Error Rate (BER). The FEC module is capable of correcting a certain number of errors per unit of time, and its efficacy is measured by its Coding Gain. The Coding Gain of the FEC module is calculated as the ratio between the SNR required for achieving the BER at the output of the FEC module, without using the FEC, and the SNR at the input to the FEC module.
A FEC module with a higher Coding Gain means that the received coded signal can have a lower SNR without disrupting output signal integrity. With high Coding Gain, a significant rate of bit error can appear at the input of the FEC module before errors appear at the FEC module output.
For example, conventional FEC modules used in wire line communications, the KR4 FEC and KP4 FEC, have respectively 5.8 dB and 7.2 dB of Coding Gain when the FEC input BER levels are below 1E-5. This means the BER at the output of these FEC modules can be below 10E-17 with BERs on the order of 1E-4 and 1E-5, respectively, at their inputs.
Another concern with SerDes design is that, as signal integrity is reduced and link margins shrink, the fine tuning of system parameters becomes more important in order to optimize link quality and other system characteristics, yet at the same time the sensitivity and narrow link margins of the system makes such tuning more difficult when the link is in use because of the risk of disrupting the integrity of the signal.
Accordingly, SerDes systems presently use two methods for optimization of system parameters: SerDes Calibration, which calibrates the system parameters based on characteristics of the SerDes blocks themselves, and SerDes Adaptation, which monitors the performance of the input/output link and adapts the system to characteristics of the link as well as characteristics of the SerDes blocks. These methods are used in a typical SerDes to optimize the BER at the receiving end.
SerDes Calibration is typically carried out when a link starts up. It is not dependent on the link. It adjusts a variety of system parameters in the circuitry as follows: a quantity (e.g. voltage, current, or phase) is measured via a measuring circuit, such as an analog-to-digital converter (ADC), and action is taken to increase or decrease that quantity until the quantity reaches a target level. The quantities being measured may be, for example, voltage offsets, timing offsets, and/or current. All of these system parameters are calibrated independently from the BER at the receiver. Calibrations are carried out with closed loop state machines that aim to reach a design target for a certain voltage or current. The assumption built into the design of the SerDes is that if all the system parameters are calibrated to the target point, the BER will be minimized.
SerDes Adaptation is typically carried out at link startup time, as well as continuously in the background during link operation while data is being transmitted. SerDes Adaptation depends upon the link itself. It typically involves the optimization of continuous time and discrete time filters that are used to minimize inter-symbol interference (ISI) due to channel insertion loss. In more sophisticated systems, SerDes Adaptation may include other system parameters, such as sampling voltage and timing offset, which may different for different channels. SerDes Adaptation typically includes: transmitter Finite Impulse Response (FIR), which is typically carried out only at start up via standard link training protocols; receiver continuous time linear equalization (CTLE), which is typically carried out using eye monitoring metrics; and decision feedback equalization (DFE), which is typically carried out using a least mean square (LMS) algorithm. As temperature, voltage and other environmental conditions vary in time, SerDes Adaptation keeps optimizing the transceiver system parameters in an attempt to maintain signal integrity.
While maintaining signal integrity is the primary goal of optimizing system parameters, it is also desirable to minimize the use of power without losing signal integrity. Power consumption is therefore one of the system parameters that should be minimized when optimizing for signal integrity.
When performing power optimization, it is necessary to determine the link margin. The power committed to equalization can be reduced as long as a sufficient link margin is maintained.
One way to monitor link margin is to monitor BER of the received signal. However, this technique has two major drawbacks. First, in a low loss communication channel, a very low BER level requires measuring BER over a long period of time to calculate an accurate average BER. Second, when measured for short periods of time, the BER metric may experience fluctuations resulting from its statistical nature, making it difficult to discriminate between two configurations which produce similar BER.